Hello,
I'm planning to use the RP2040 versatile PIO to drive a parallel port display. It should have a timing roughly like in the picture:
I'm using one PIO state machine to generate the clock and another state machine to generate the parallel output.
I am going to have this DATA signal wait for the rising edge of the HSYNC signal and start outputting data after a delay of t_HBP time. I experimented with the following program, here the clock frequency is set to a lower value for debugging. But the result is very strange.
Running this code, there is only output on the Clock pin and no output on the DATA pins. However, when I changed the porch cycles from 118 to 30, it magically worked.
But as you can also see from the results in the logic analyzer, it's not what I expected, at least not enough T_bph (expected to be 30 cycles in changed code) at all before the DATA bus output.
What's even more strange is that even without putting hsync_pin.value(0) in the loop, and just leaving hsync_pin.value(1), there will still be output on the DATA bus. But then there is no rising edge at all for HSYNC, so why does the DATA bus continue to produce output?
I hope someone with expertise can help me understand what's going on here or what I should do?
I'm planning to use the RP2040 versatile PIO to drive a parallel port display. It should have a timing roughly like in the picture:
I'm using one PIO state machine to generate the clock and another state machine to generate the parallel output.
I am going to have this DATA signal wait for the rising edge of the HSYNC signal and start outputting data after a delay of t_HBP time. I experimented with the following program, here the clock frequency is set to a lower value for debugging. But the result is very strange.
Code:
import rp2import timefrom machine import Pinfrom rp2 import PIO, StateMachine, asm_pio# PIO clock lane# four clock cycles, 2 low, 2 high@rp2.asm_pio(set_init=rp2.PIO.OUT_LOW)def parallel_bus_clk_pio(): wrap_target() set(pins, 0) [0] set(pins, 1) [0] wrap()#outputs a byte through the parallel bus@asm_pio(out_init=(PIO.OUT_LOW,) * 8, out_shiftdir=PIO.SHIFT_RIGHT)def parallel_bus_pio(): wrap_target() # wait for hsync to pulse wait(0, pin, 13) wait(1, pin, 13) # hsync back porch 118 cycles set(y, 118) label("back_porch") nop() jmp(y_dec, "back_porch") # 2 clocks per cycle # data valid for 900 transitions set(x, 900) label("data_valid") pull() [0] out(pins, 8) [0] jmp(x_dec, "data_valid") [1] wrap()sm_bus = rp2.StateMachine(0, parallel_bus_pio, freq=54_000, out_base=(2))sm_clk = rp2.StateMachine(1, parallel_bus_clk_pio, freq=54_000, set_base=Pin(11))hsync_pin = Pin(13)hsync_pin.value(0)sm_clk.active(1)sm_bus.active(1)while True: time.sleep_us(1000) hsync_pin.value(0) time.sleep_us(100) hsync_pin.value(1) time.sleep_us(20) for i in range(900): sm_bus.put(i)Running this code, there is only output on the Clock pin and no output on the DATA pins. However, when I changed the porch cycles from 118 to 30, it magically worked.
Code:
# hsync back porch 118 cycles set(y, 30)#################### Change from 118 to 30 label("back_porch") nop() jmp(y_dec, "back_porch") # 2 clocks per cycle But as you can also see from the results in the logic analyzer, it's not what I expected, at least not enough T_bph (expected to be 30 cycles in changed code) at all before the DATA bus output.
What's even more strange is that even without putting hsync_pin.value(0) in the loop, and just leaving hsync_pin.value(1), there will still be output on the DATA bus. But then there is no rising edge at all for HSYNC, so why does the DATA bus continue to produce output?
Code:
while True: time.sleep_us(1000) #hsync_pin.value(0)#################### Delete this line time.sleep_us(100) hsync_pin.value(1) time.sleep_us(20) for i in range(900): sm_bus.put(i)Statistics: Posted by b0wen — Sun Apr 07, 2024 10:55 am — Replies 1 — Views 32