Hello, I'm trying to implement a simple 10us timer counter with PIO. I'm using a register decrement to achieve the delay I need between pushes to the FIFO. The problem I'm having is the depth of the PIO FIFO. Since it can store 4 x 32bit words, the core is not getting the latest timer value and even worse: if the FIFO is full, no value is written to it until the core actually gets a value and makes room for another. What I'm trying to achieve is:
The PIO RX FIFO holds a single 32-bit value.
The state machine writes a single 32-bit value to the FIFO, overwriting the previous value if it was not empty.
Is there a way I can get this to work in the way I want? I know I can use to clear FIFOs from the outside, but I need to clear it from inside the state machine so that the FIFO holds one value at most.
Help is much appreciated.
The PIO RX FIFO holds a single 32-bit value.
The state machine writes a single 32-bit value to the FIFO, overwriting the previous value if it was not empty.
Is there a way I can get this to work in the way I want? I know I can use
Code:
pio_sm_clear_fifos()Help is much appreciated.
Statistics: Posted by EvilGears — Wed Jul 02, 2025 4:22 pm — Replies 0 — Views 25