I have a 800x1280 4-lane ili9881c based DSI display. On the left side (vertical oriented) I have 2 pixels which should be on the right side.
This are the parameters from the manufacturer:I have dialed-in the clock like this into the drm_display_mode struct:On CM5, this works well.
But on CM4 there is the mentioned 2-Pixel shift/wrap to the left of the display.
If I understand the post viewtopic.php?p=2115052#p2115052 correctly, plld_dsi1 should correlate with the mipi channel speed.
This is what it reports on clk_summary:Any idea how to fix this?
This are the parameters from the manufacturer:
Code:
#VFP 16#VBP 24#VSA 8#HFP 80#HBP 80#HSA 20#frame rate = 60Hz#PCLK = 78.086MHz#MIPI_CLK = 468Mbps (MIPI channel speed)#dsi.PLL_CLOCK = 234Mbps (MTK platform speed)Code:
+.clock = 78086,+.hdisplay = 800,+.hsync_start = 800 + 80,+.hsync_end = 800 + 80 + 20,+.htotal = 800 + 80 + 20 + 80,+.vdisplay = 1280,+.vsync_start = 1280 + 16,+.vsync_end = 1280 + 16 + 8,+.vtotal = 1280 + 16 + 8 + 24,But on CM4 there is the mentioned 2-Pixel shift/wrap to the left of the display.
If I understand the post viewtopic.php?p=2115052#p2115052 correctly, plld_dsi1 should correlate with the mipi channel speed.
This is what it reports on clk_summary:
Code:
# cat /sys/kernel/debug/clk/clk_summary | grep dsi plld_dsi1 3 3 0 500000016 0 0 50000 Y fe700000.dsi phy dsi1_ddr 0 0 0 250000008 0 0 50000 Y deviceless no_connection_id dsi1_ddr2 0 0 0 125000004 0 0 50000 Y deviceless no_connection_id dsi1_byte 1 1 0 62500002 0 0 50000 Y deviceless no_connection_id dsi1p 1 1 0 62500002 0 0 50000 Y fe700000.dsi pixel plld_dsi0 1 1 0 11718751 0 0 50000 Y deviceless no_connection_id dsi1e 1 1 0 100000003 0 0 50000 Y fe700000.dsi escape plla_dsi0 1 1 0 11718750 0 0 50000 Y deviceless no_connection_id dsi0p 0 0 0 0 0 0 50000 Y deviceless no_connection_id dsi0e 0 0 0 0 0 0 50000 Y deviceless no_connection_id Statistics: Posted by batwing — Thu Jun 19, 2025 3:53 pm — Replies 3 — Views 76