Hi,
I've been developing a multi-core app on pico, where core 1 only runs an ISR that rescales an audio buffer. I've seen lots of warning about how pico can hang/crash if you try to read from flash while it's being written. But I'm pretty certain that my ISR is only manipulating RAM. I think it ought to be possible to keep running it during a flash write -- and that would be great, because otherwise the audio glitches out.
ATM it seems that when core 0 calls save_and_disable_interrupts() and then flash_range_program(), nothing crashes, but OTOH the core 1 ISR does not fire until after the flash save finishes. It looks like either the core 1 interrupts stop firing or core 1 just pauses.
I don't have debugger access on this particular board so I don't know exactly what's happening. But I assume that save_and_disable_interrupts(), as it's being called, should only be disabling interrupts on core 0.
What I wonder is, is there anything else that would lock up core 1 during a flash write by core 0? Assuming that core 1 is not touching flash?
I guess that the ISR code is running from the XIP cache, so maybe it needs to get reloaded after the cache is flushed. But the ISR gets disabled for about 600 microseconds, which seems to be the entire duration of the flash write. The ISR is only a few hundred bytes, it should load from Flash faster than that, I think?
Just trying to theorize what's happening here. Any advice much appreciated. Thanks!
I've been developing a multi-core app on pico, where core 1 only runs an ISR that rescales an audio buffer. I've seen lots of warning about how pico can hang/crash if you try to read from flash while it's being written. But I'm pretty certain that my ISR is only manipulating RAM. I think it ought to be possible to keep running it during a flash write -- and that would be great, because otherwise the audio glitches out.
ATM it seems that when core 0 calls save_and_disable_interrupts() and then flash_range_program(), nothing crashes, but OTOH the core 1 ISR does not fire until after the flash save finishes. It looks like either the core 1 interrupts stop firing or core 1 just pauses.
I don't have debugger access on this particular board so I don't know exactly what's happening. But I assume that save_and_disable_interrupts(), as it's being called, should only be disabling interrupts on core 0.
What I wonder is, is there anything else that would lock up core 1 during a flash write by core 0? Assuming that core 1 is not touching flash?
I guess that the ISR code is running from the XIP cache, so maybe it needs to get reloaded after the cache is flushed. But the ISR gets disabled for about 600 microseconds, which seems to be the entire duration of the flash write. The ISR is only a few hundred bytes, it should load from Flash faster than that, I think?
Just trying to theorize what's happening here. Any advice much appreciated. Thanks!
Statistics: Posted by mykle — Mon Jul 15, 2024 11:04 pm — Replies 0 — Views 29